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1 features ? multifunction charge/discharge counter ? resolves signals less than 12.5 v ? internal offset calibration im - proves accuracy ? 1024 bits of nvram configured as 128x8 ? internal temperature sensor for self-discharge estimation ? single-wire serial interface ? dual operating modes: - operating: <80 a - sleep: <10 a ? reg output for low-cost mi- croregulation ? internal timebase eliminates ex- ternal components ? 8-pin tssop or soic allows bat- tery pack integration general description the bq2018 is a low-cost charge/dis - charge counter peripheral packaged in an 8-pin tssop or soic. it works with an intelligent host controller, pro - viding state-of-charge information for rechargeable batteries. the bq2018 measures the voltage drop across a low-value series sense resistor between the negative termi - nal of the battery and the battery pack ground contact. by using the ac - cumulated counts in the charge, discharge, and self-discharge regis - ters, an intelligent host controller can determine battery state-of-charge in - formation. to improve accuracy, an offset count register is available. the system host controller is responsible for the register maintenance by reset- ting the charge in/out and self- discharge registers as needed. the bq2018 also features 128 bytes of nvram registers. the upper 13 bytes of nvram contain the capac - ity monitoring and status informa - tion. the rbi input operates from an external power storage source such as a capacitor or a series cell in the battery pack, providing register nonvolatility for periods when the battery is shorted to ground or when the battery charge state is not suffi - cient to operate the bq2018. during this mode, the register backup cur - rent is less than 100na. packaged in an 8-pin tssop or soic, the bq2018 is small enough to fit in the crevice between two a- size cells or within the width of a prismatic cell. reg regulator output v cc supply voltage input v ss ground hdq data input/output 1 pn-201801.eps 8-pin tssop or narrow soic 2 3 4 8 7 6 5 reg v cc v ss hdq wake sr1 sr2 rbi wake wake-up output sr1 current sense input 1 sr2 current sense input 2 rbi register backup input pin connections pin names bq2018 power minder? ic slus003?june 1999 c
pin descriptions reg regulator output reg is the output of the operational trans - conductance amplifier (ota) that drives an external pass n-channel jfet to provide an optional regulated supply. the supply is regulated at 3.7v nominal. v cc supply voltage input when regulated by the reg output, v cc is 3.7v 200mv. when the reg output is not used, the valid operating range is 2.8v to 5.5v. v ss ground sr1? sr2 current sense inputs the bq2018 interprets charge and discharge activity by monitoring and integrating the voltage drop (v sr ) across pins sr1 and sr2. the sr1 input connects to the sense resistor and the negative terminal of the battery. the sr2 input connects to the sense resistor and the negative terminal of the pack. v sr1 v sr2 indicates charge. the effective voltage drop, v sro , as seen by the bq2018, is v sr +v os . valid input range is 200mv. hdq data input/output this bi-directional input/output communi - cates the register information to the host system. hdq is open drain and requires a pullup/down resistor in the battery pack to disable/enable sleep mode if the pack is re - moved from the system. rbi register backup input this input maintains the internal register states during periods when v cc is below the minimum operating voltage. wake wake-up output when asserted, this output is used to indi - cate that the charge or discharge activity is above a programmed minimal level. functional description general operation a host can use the bq2018 internal counters and timers to measure battery state-of-charge, estimate self- discharge, and calculate the average charge and dis - charge current into and out of a rechargeable battery. the bq2018 needs an external host system to perform all register maintenance. using information from the bq2018, the system host can determine the battery state-of-charge, estimate self-discharge, and calculate the average charge and discharge currents. during pack storage periods, the use of an internal temperature sen - sor doubles the self-discharge count rate every 10 above 25c. to reduce cost, power to the bq2018 may be derived using a low-cost external fet in conjunction with the reg pin. the bq2018 operating current is less than 80 a. when the hdq line remains low for greater than ten seconds and v sro (v sr +v os where v sr is the voltage drop be - tween sr1 and sr2 and v os is the offset voltage) is below the programmed minimal level (wake is in high z), the bq2018 enters a sleep mode of <10 a where all opera- tions are suspended. hdq transitioning high reinitiates the bq2018. a register is available to store the calculated offset, allow- ing current calibration. the offset cancellation register is written by the bq2018 during pack assembly and is avail- able to the host system to adjust the current measure- ments. by adding or subtracting the offset value stored in the ofr, the true charge and discharge counts can be calculated to a high degree of certainty. figure 1 shows a block diagram of the bq2018, and table 1 outlines the bq2018 operational states. reg output the bq2018 can operate directly from three or four nickel-chemistry cells or a single li-ion cell as long as v cc is limited to 2.8 to 5.5v. to facilitate the power sup - ply requirements of the bq2018, a reg output is present to regulate an external low-threshold n-jfet. a micro - power v cc source for the bq2018 can inexpensively be built using this fet. 2 bq2018
note: v sro is the voltage difference between sr1 and sr2 plus the offset voltage v os . 3 bd201801.eps differential dynamically balanced vfc system i/o and control ram and counters 128 x 8 counter control temperature- compensated precision oscillator bandgap voltage reference temperature sensor sr1 sr2 hdq rbi v dd (internal) optional (external) ds g reg v cc v ss timer calibration and power control wake v ref figure 1. bq2018 block diagram bq2018 hdq pin dcr/ccr/scr woe wake operating state hdq high yes |v sro | > v woe low normal hdq high yes |v sro | < v woe high z normal hdq low no |v sro | < v woe high z sleep table 1. operational states
4 rbi input the rbi input pin is used with a storage capacitor or ex- ternal supply to provide back-up potential to the internal ram when v cc drops below 2.4v. the maximum dis- charge current is 100na in this mode. the bq2018 out- puts v cc on rbi when the supply is above 2.4v, so a di- ode is required to isolate an external supply. charge/discharge count operation table 2 shows the main counters and registers of the bq2018. the bq2018 accumulates charge and discharge counts into two main count registers, the discharge count register (dcr) and the charge count register (ccr). the bq2018 produces charge and discharge counts by sensing the voltage difference across a low- value resistor between the negative terminal of the bat- tery pack and the negative terminal of the battery. the dcr or ccr counts depending on the signal between sr1 and sr2. during discharge, the dcr and the discharge time counter (dtc) are active. if v sr1 is less than v sr2 , indi - cating a discharge, the dcr counts at a rate equivalent to 12.5 v every hour, and the dtc counts at a rate of 1 count/0.8789 seconds (4096 counts per 1 hour). for exam - ple, a -100mv signal produces 8000 dcr counts and 4096 dtc counts each hour. the amount of charge removed from the battery can easily be calculated. bq2018 table 2. bq2018 counters name description range ram size dcr discharge count register v sr1 < v sr2 (max. =-200mv) 12.5 vh increments 16-bit ccr charge count register v sr1 >v sr2 (max. = +200mv) 12.5 vh increments 16-bit scr self-discharge count register 1 count/hour @ 25c 16-bit dtc discharge time counter 1 count/0.8789s default 1 count/225s if std is set 16-bit ctc charge time counter 1 count/0.8789s default 1 count/225s if stc is set 16-bit mode/ woe mode/ wake output enable ? 8-bit rbi sr2 sr1 wake hdq vss vcc reg bq2018 u1 1 2 3 45 6 7 8 c1 vcc sst113 q1 bat+ bzx84c5v6 d1 2 hdq bzx84c5v6 d2 2 100 r5 c4 c2 c3 bav99 d3 1m d s r4 rbi pack- bat- 1w 0.05 r1 100k r3 100k r2 wake 1k r6 vcc 0.01 f 0.1 f 0.1 f 0.1 f 0.1 f c5 2018typap.eps figure 2. typical application
5 during charge, the ccr and the charge time counter (ctc) are active. if v sr1 is greater than v sr2 , indicating a charge, the ccr counts at a rate equivalent to 12.5 v every hour, and the ctc counts at a rate of 1 count/0.8789 seconds. for example, a +100mv signal pro- duces 8000 ccr counts and 4096 ctc counts each hour. the amount of charge added to the battery can easily be calculated. the dtc and the ctc are 16-bit registers, and roll over beyond ffffh. if a rollover occurs, the corresponding bit in the mode/woe register is set, and the counter will sub - sequently increment at 1/256 of the normal rate (16 counts/hr.). whenever the signal between sr1 and sr2 is above the wakeup output enable (woe) threshold and the hdq pin is high, the bq2018 is in its full operating state. in this state, the dcr, ccr, dtc, ctc, and scr are fully operational, and the wake output is low. during this mode, the internal ram registers of the bq2018 may be accessed over the hdq pin, as described in the section ?communicating with the 2018.? if the signal between sr1 and sr2 is below the woe threshold (refer to the wake section for details) and hdq remains low for greater than 10 seconds, the bq2018 enters a sleep mode where all register counting is suspended. the bq2018 remains in this mode until hdq returns high. for self-discharge calculation, the self-discharge count register (scr) counts at a rate equivalent to 1 count every hour at a nominal 25c and doubles approximately every 10c up to 60c. the scr count rate is halved every 10 c below 25 c down to 0 c. the value in scr is useful in determining an estimation of the battery self- discharge based on capacity and storage temperature conditions. the bq2018 may be programmed to measure the voltage offset between sr1 and sr2 during pack assembly or at any time by invoking the calibration mode. the offset register (ofr) is used to store the bq2018 offset. the 8- bit 2?s complement value stored in the ofr is scaled to the same units as the dcr and ccr, representing the amount of positive or negative offset in the bq2018. the maximum offset for the bq2018 is specified as 500 v. care should be taken to ensure proper pcb layout. us - ing ofr, the system host can cancel most of the effects of bq2018 offset for greater resolution and accuracy. figure 3 shows the bq2018 register address map. the bq2018 uses the upper 13 locations. the remaining memory can store user-specific information such as chemistry, serial number, and manufacturing date. wake output this output is used to inform the system that the voltage difference between sr1 and sr2 is above or below the wake output enable (woe) threshold programmed in the mode/woe register. when the voltage difference between sr1 and sr2 is below v woe , the wake output goes into high z and remains in this state until the dis - charge or charge current increases above the specified value. the mode/woe resets to 0eh after a power-on reset. v woe is set by dividing 3.84mv by a value be - tween 1 and 7 (1?7h) according to table 3. bq2018 7f 7e 7d 7c 7b 7a 79 78 77 76 75 74 73 user ram discharge count high byte discharge count low byte charge count high byte charge count low byte self-discharge high byte self-discharge low byte discharge time high byte discharge time low byte charge time high byte charge time low byte mode/wake output enable temperature/clear offset register fg201801.eps 00 73 72 7f figure 3. address map
table 3. woe thresholds woe 3?1 (hex) v woe (mv) 0h n/a 1h 3.840 2h 1.920 3h 1.280 4h 0.960 5h 0.768 6h 0.640 7h* 0.549 * default value after por. temperature the bq2018 has an internal temperature sensor which is used to set the value in the temperature register (tmp/clr) and set the self-discharge count rate value. the register reports the temperature in 8 steps of 10c from <0c to >60c as table 4 specifies. the bq2018 tem- perature sensor has typical accuracy of 2 cat 25 c. see the tmp/clr register description for more details. clear register the host system is responsible for register maintenance. to facilitate this maintenance, the bq2018 has a clear register (tmp/clr) designed to reset the specific coun- ter or register pair to zero. the host system clears a reg - ister by writing the corresponding register bit to 1. when the bq2018 completes the reset, the corresponding bit in the tmp/clr register is automatically reset to 0, which saves the host an extra write/read cycle. clearing the dtc register clears the std bit and sets the dtc count rate to the default value of 1 count per 0.8789s. clearing the ctc register clears the stc bit and sets the ctc count rate to the default value of 1 count per 0.8789s. calibration mode the system can enable bq2018 v os calibration by setting the calibration bit in the mode/woe register (bit 6) to 1. the bq2018 then enters calibration mode when the hdq line is low for greater than 10 seconds and when the signal between sr1 and sr2 is below v woe . cau- tion: take care to ensure that no low-level exter- nal signal is present between sr1 and sr2 because this affects the calibration value that the bq2018 calculates. if hdq remains low for one hour and |v sr |60 7h 16 table 4. temperature steps
7 symbol register name loc. (hex) read/ write control field 7(msb) 654321 0(lsb) cmdr command register - write w/r ad6 ad5 ad4 ad3 ad2 ad1 ad0 dcrh discharge count register high byte 7f read dcrh7 dcrh6 dcrh5 dcrh4 dcrh3 dcrh2 dcrh1 dcrh0 dcrl discharge count register low byte 7e read dcrl7 dcrl6 dcrl5 dcrl4 dcrl3 dcrl2 dcrl1 dcrl0 ccrh charge count register high byte 7d read ccrh7 ccrh6 ccrh5 ccrh4 ccrh3 ccrh2 ccrh1 ccrh0 ccrl charge count register low byte 7c read ccrl7 ccrl6 ccrl5 ccrl4 ccrl3 ccrl2 ccrl1 ccrl0 scrh self-discharge count register high byte 7b read scrh7 scrh6 scrh5 scrh4 scrh3 scrh2 scrh1 scrh0 scrl self-discharge count register low byte 7a read scrl7 scrl6 scrl5 scrl4 scrl3 scrl2 scrl1 scrl0 dtch discharge time count high byte 79 read dtch7 dtch6 dtch5 dtch4 dtch3 dtch2 dtch1 dtch0 dtcl discharge time count low byte 78 read dtcl7 dtcl6 dtcl5 dtcl4 dtcl3 dtcl2 dtcl1 dtcl0 ctch charge time count high byte 77 read ctch7 ctch6 ctch5 ctch4 ctch3 ctch2 ctch1 ctch0 ctcl charge time count low byte 76 read ctcl7 ctcl6 ctcl5 ctcl4 ctcl3 ctcl2 ctcl1 ctcl0 mode/ woe mode/ wake- up output enable 75 read/ write ovrdq cal stc std woe3 woe2 woe1 0 tmp/clr tempera - ture/clear register 74 read/ write tmp2 tmp1 tmp0 ctc dtc scr ccr dcr ofr offset register 73 read/ write ofr7 ofr6 ofr5 ofr4 ofr3 ofr2 ofr1 ofr0 ram user memory 72-00 read/ write ------- - notes: 1. mode/woe register bit 0 is set to zero at startup and should not be written to 1 for proper bq2018 operation. 2. ofr value is in two?s complement. table 5. bq2018 command and status registers bq2018
8 low-power mode until hdq goes high, indicating an ex - ternal system is ready to access the bq2018. if hdq transitions high prior to completion of the v os calculation or if |v sr |>v woe , then the calibration cycle is reset. the bq2018 then postpones the calibration cycle until the conditions are met. the calibration bit does not reset to zero until a valid calibration cycle is completed. the re - quirement for hdq to remain low for the calibration cy - cle can be disabled by setting the ovrdq bit to 1. in this case, calibration continues as long as |v sr | 9 of the discharge, and are incremented whenever v sr1 < v sr2 . these registers continue to count beyond ffffh, so proper register maintenance should be done by the host system. the tmp/clr register is used to force the reset of both the dcrh and dcrl to zero. charge count registers (ccrh/ccrl) the ccrh high-byte register (address = 7dh) and the ccrl low-byte register (address = 7ch) contain the count of the charge, and are incremented whenever v sr1 > v sr2 . these registers continue to count beyond ffffh, so proper register maintenance should be done by the host system. the tmp/clr register is used to force the reset of both the ccrh and ccrl to zero. self-discharge count registers (scrh/scrl) the scrh high-byte register (address = 7bh) and the scrl low-byte register (address = 7ah) contain the self- discharge count. this register is continually updated whenever the bq2018 is in its normal operating mode. the counts in these registers are incremented based on time and temperature. the scr counts at a rate of 1 count per hour at 20?30c and doubles every 10c to greater than 60c (16 counts/hour). the count will half every 10c below 20?30c to less than 0c (1 count/8 hours). these registers continue to count beyond ffffh, so proper register maintenance should be done by the host system. the tmp/clr register is used to force the reset of both the scrh and scrl to zero. discharge time count registers (dtch/dtcl) the dtch high-byte register (address = 79h) and the dtcl low-byte register (address = 78h) are used to deter - mine the length of time the v sr1 v sr2 indicating a charge. the counts in these registers are incremented at a rate of 4096 counts per hour. if the ctch/ctcl regis - ters continue to count beyond ffffh, the stc bit is set in the mode/woe register indicating a rollover. once set, dtch and dtcl increment at a rate of 16 counts per hour. note: if a second rollover occurs, stc is cleared. access to the bq2018 should be timed to clear ctch/ctcl more often than every 170 days. the tmp/clr register is used to force the reset of both the ctch and ctcl to zero. mode/wake-up enable register the mode/woe register (address = 75h) contains the calibration, wakeup enable information, and the stc and std bits as described below. the override dq(ovrdq) bit (bit 7) is used to override the requirement for hdq to be low prior to initiating v os calibration. this bit is normally set to zero. if ovrdq is written to one, the bq2018 begins offset calibration when |v sr | the slow time charge (stc) and slow time discharge (std) flags indicate if the ctc or dtc registers have rolled over beyond ffffh. stc set to 1 indicates a ctc rollover; std set to 1 indicates a dtc rollover. the stc and std locations are mode/woe bits 765 4 3 2 1 0 - - stc std - - - - where stc/std is 0 no rollover 1 rollover occurred in the corresponding ctc/dtc register. the wake up output enable (woe) bits (bits 3?1) are used to set the wake-up enable signal level. whenever |v sro | 60c and clear the various count registers. the values of the tmp0?tmp2 (bits 5?7) denote the current temperature step sense by the bq2018 as outlined in table 4. the bq2018 temperature sense is trimmed to 2 c typical ( 4c maximum). the tmp2?0 locations are tmp/clr bits 76543210 tmp2 tmp1 tmp0 - - - - - where tmp2?0 is the temperature step sensed by this bq2018. the clear bits (bits 0?4) are used to reset the various bq2018 counters and stc and std bits to zero. writing the bits to 1 resets the corresponding register to 0. the clear bit resets to 0 indicating a successful register reset. each clear bit is independent, so it is possible to clear the dcrh/dcrl registers without affecting the values in any other bq2018 register. the high-byte and low-byte registers are both cleared when the corresponding bit is written to 1 per the figure below. 10 bq2018 send host to bq-hdq cdmr send host to bq-hdq or receive from bq-hdq data address break lsb bit0 r/w msb bit7 td201807.eps start-bit address-bit/ data-bit stop-bit t rr t rsps figure 5. communications frame example
11 the clear bit locations are tmp/clr bits 76543 2 1 0 - - - ctc dtc scr ccr dcr where: ctc bit (bit 4) resets both the ctch and ctcl registers and the stc bit to 0. the dtc bit (bit 3) resets both the dtch and dtcl registers and the std bit to 0. the scr bit (bit 2) resets both the scrh and scrl reg - isters to 0. the ccr bit (bit 1) resets both the ccrh and ccrl registers to 0. the dcr bit (bit 0) resets both the dcrh and dcrl registers to 0. offset register (ofr) the ofr register (address = 73h) is used to store the cal - culated v os of the bq2018. the ofr value can be used to cancel the voltage offset between v sr1 and v sr2 . the up/down offset counter is centered at zero. the actual off - set is an 8-bit two?s complement value located in ofr. the ofr locations are ofr bits 76543210 ofr7 ofr6 ofr5 ofr4 ofr3 ofr2 ofr1 ofr0 where ofr7 is 1 discharge 0 charge bq2018
12 absolute maximum ratings symbol parameter minimum maximum uni t notes v cc relative to v ss -0.3 +6.0 v hdq relative to v ss -0.3 +6.0 v all other pins v ss -0.3v v cc +3.0v v i reg reg to v ss 1.0 ma v sr1 / v sr2 relative to v ss -0.3 +6.0 v a 100k ? series resistor is recommended to protect sr1 / sr2 in case of a shorted battery. t opr operating temperature - 20 +70 c note: permanent device damage may occur if absolute maximum ratings are exceeded. functional opera - tion should be limited to the recommended dc operating conditions detailed in this data sheet. expo - sure to conditions beyond the operational limits for extended periods of time may affect device reliability. dc electrical characteristics (t a =t opr ) symbol parameter minimum typical maximum unit notes v cc supply voltage 2.8 4.25 5.5 v reg = no connect 3.5 3.7 3.9 v v cc derived from reg, note 3 i cc operating current -6070 av cc,hdq = 3.7v -7080 av cc,hdq = 5.5v i cc2 sleep - - 10 av cc = 5.5v i rbi rbi current - - 100 na v cc < 2.4v v sr sense resistor input -200 - 200 mv v sr1 v sr2 = charge note 2 r sr sr1 / sr2 input impedance 10 - - m ? -200mv < v sr < 200mv i ol open-drain sink current - - 2.0 ma v ol =v ss + 0.3v wake , hdq v ihdq hdq input high 2.5 - - v v ildq hdq input low - - 0.8 v notes: 1. all voltages relative to v ss . 2. v sr1 / sr2 +v os .v os is affected by pc board layout. follow proper layout guidelines for optimal performance. 3. can be guaranteed by design when using an sst108 or equivalent jfet. bq2018
13 bq2018 performance characteristics (t a =t opr ) symbol parameter typical maximum unit notes v os offset voltage 500 v voltage offset between sr1 and sr2 osc timer accuracy 1.5 3.0 % v cc =3.5 - 3.9v (t a = 0?70 c) inr integrated non- repeatability error 0.5 1.0 % measured repeatability given similar operating conditions inl integrated non-linearity 1.0 2.0 % add 0.05% per c above or below 25 c and 0.5% per volt above or be - low 3.7v. standard serial communication timing specification (t a =t opr ) symbol parameter minimum typical maximum unit notes t cych cycle time, host to bq2018 (write) 190 - - s t cycb cycle time, bq2018 to host (read) 190 205 250 s t strh start hold, host to bq2018 (write) 5 - - ns t strb start hold, bq2018 to host (read) 32 - - s t dsu,b data setup - - 50 s t dh data hold 90 - - s t dv data valid - - 80 s t ssub stop setup (bq2018 to host) - - 95 s t ssu stop setup (host to bq2018) - - 145 s t b break 190 - - s t br break recovery 40 - - s t rsps response time, bq2018 to host 190 - 320 s t rr read recovery 40 - - s host read to next cycle
14 t b t br break timing t strh t dsu t dh t ssu t cych write "1" write "0" host to bq2018 t strb t dsub t dv t ssub t cycb read "1" read "0" bq2018 to host bq2018
15 bq2018 8-pin soic narrow ~ sn package suffix dimension millimeters inches min. max. min. max. a 1.52 1.78 0.060 0.070 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.18 0.25 0.007 0.010 d 4.70 5.08 0.185 0.200 e 3.81 4.06 0.150 0.160 e 1.14 1.40 0.045 0.055 h 5.72 6.22 0.225 0.245 l 0.38 0.89 0.015 0.035
16 bq2018 dimension millimeters inches min. max. min. max. a - 1.10 - 0.043 a1 0.05 0.15 0.002 0.006 b 0.18 0.30 0.007 0.012 c 0.09 0.18 0.004 0.007 d 2.90 3.10 0.115 0.122 e 4.30 4.48 0.169 0.176 e 0.65bsc 0.0256bsc h 6.25 6.50 0.246 0.256 l 0.50 0.70 0.020 0.028 notes: 1. controlling dimension: millimeters. inches shown for reference only. 2 'd' and 'e' do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm per side 3 each lead centerline shall be located within 0.10mm of its exact true position. 4. leads shall be coplanar within 0.08mm at the seating plane. 5 dimension 'b' does not include dambar protrusion. the dambar protrusion(s) shall not cause the lead width to exceed 'b' maximum by more than 0.08mm. 6 dimension applies to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. 7 'a1' is defined as the distance from the seating plane to the lowest point of the package body (base plane). 8-pin tssop ~ ts package suffix
17 bq2018 change no. page no. description nature of change 1 all 2 12 clarification of absolute maximum pin ratings note: change 1 = jan. 1999 b changes to final from dec. 1998 preliminary data sheet. change 2 = june 1999 c changes from jan. 1999 b. data sheet revision history
18 bq2018 ordering information bq2018 package option: sn = 8-pin narrow soic ts = 8 pin tssop temperature range: blank = commercial (-20 to +70c) device: bq2018 power minder ic
19 notes
package option addendum www.ti.com 1-jul-2010 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) bq2018sn-e1 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim request free samples bq2018sn-e1tr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim purchase samples BQ2018SN-E1TRG4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim purchase samples bq2018ts-e1 active tssop pw 8 150 green (rohs & no sb/br) cu nipdau level-2-260c-1 year request free samples bq2018ts-e1tr active tssop pw 8 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year purchase samples bq2018ts-e1trg4 active tssop pw 8 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year purchase samples (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 1-jul-2010 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant bq2018sn-e1tr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 bq2018ts-e1tr tssop pw 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 q1 package materials information www.ti.com 30-jun-2010 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) bq2018sn-e1tr soic d 8 2500 346.0 346.0 29.0 bq2018ts-e1tr tssop pw 8 2000 346.0 346.0 29.0 package materials information www.ti.com 30-jun-2010 pack materials-page 2
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